1076.6-1999 IEEE Standard for VHDL Register Transfer Level

A regular syntax and semantics for VHDL sign in move point (RTL) synthesis is outlined. The subset of IEEE 1076 (VHDL) that's appropriate for RTL synthesis is outlined, in addition to the semantics of that subset for the synthesis area.

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Additional info for 1076.6-1999 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis

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All rights reserved. 3 Package TEXTIO The subprograms defined in package TEXTIO shall not be supported. 58 Copyright © 2000 IEEE. All rights reserved. 6-1999 Annex A (informative) Syntax summary This annex summarizes the VHDL syntax that is supported. abstract_literal ::= decimal_literal | based_literal access_type_definition ::= access subtype_indication actual_designator ::= expression | signal_name | variable_name | file_name | open actual_parameter_part ::= parameter_association_list actual_part ::= actual_designator | function_name( actual_designator ) | type_mark( actual_designator ) adding_operator ::= + | - | & aggregate ::= ( element_association {, element_association} ) alias_declaration ::= alias alias_designator [: subtype_indication] is name [signature]; alias_designator ::= identifier | character_literal | operator_symbol allocator ::= new subtype_indication | new qualified_expression architecture_body ::= architecture identifier of entity_name is architecture_declarative_part begin architecture_statement_part ] end [ architecture ] [ architecture_simple_name ] ; architecture_declarative_part ::= { block_declarative_item } architecture_statement_part ::= { concurrent_statement } array_type_definition ::= unconstrained_array_definition | constrained_array_definition assertion ::= assert condition [ report expression ] [ severity expression ] Copyright © 2000 IEEE.

All rights reserved. 2 Selected signal assignments selected_signal_assignment ::= with expression select target <= options selected_waveforms ; selected_waveforms ::= { waveform when choices , } waveform when choices Supported: — — Selected_signal_assignment Selected_waveforms Ignored: — Options Selected signal assignments that satisfy either of the following conditions shall not be supported: a) b) The selected waveforms contain a reference to one or more elements of the target signal. 2. 6 Component instantiation statement component_instantiation_statement ::= instantiation_label: instantiated_unit [ generic_map_aspect ] [ port_map_aspect ] ; instantiated_unit ::= [component] component_name | entity entity_name [( architecture_name )] | configuration configuration_name Supported: — — Component_instantiation_statement Instantiated_unit Not supported: — — Entity and configuration forms of instantiated unit Reserved word component Copyright © 2000 IEEE.

All rights reserved. 2 Process statement process_statement ::= [ process_label: ] [ postponed ] process [ ( sensitivity_list ) ] [ is ] process_declarative_part begin process_statement_part end process [process_label] ; process_declarative_part ::= { process_declarative_item } process_declarative_item ::= subprogram_declaration | subprogram_body | type_declaration | subtype_declaration | constant_declaration | variable_declaration | file_declaration | alias_declaration | attribute_declaration | attribute_specification | use_clause | group_template_declaration | group_declaration process_statement_part ::= { sequential_statement } Supported: — — — — — Process_statement Sensitivity_list Process_declarative_part Process_declarative_item Process_statement_part Ignored: — — — File_declaration Alias_declaration User-defined attribute declarations and their specifications Not supported: — Reserved words postponed and is — Group_template_declaration — Group_declaration 50 Copyright © 2000 IEEE.

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